Experimental 36-core chip spurs speed test at MIT
Experimental 36-core chip spurs speed test at MIT. The chip is designed to reduce the number of cycles required to execute tasks by enabling data transfers between cores and cache in a more coherent manner, said Bhavya Daya, a Ph.D.
Experimental 36-core chip spurs speed test at MIT. The chip is designed to reduce the number of cycles required to execute tasks by enabling data transfers between cores and cache in a more coherent manner, said Bhavya Daya, a Ph.D.
Source: www.computerworld.com
